Experience the latest Rambus PCI Express (PCIe) 6.0 IP solutions at the PCI-SIG Developers Conference in Santa Clara, CA. Witness demos of the 64 Gigatransfers per second (GT/s) PCIe 6.0 PHY and Controller IP, which offer high performance, low power, and an area-efficient footprint for compute-intensive workloads such as data center, AI/ML, and HPC applications.
The Rambus PCIe 6.0 Interface Subsystem, consisting of the PHY and Controller, has been fully optimized to meet the demands of advanced heterogenous computing architectures. The PCIe Controller features an Integrity and Data Encryption (IDE) engine that is dedicated to protecting the PCIe links and the valuable data transferred over them. The PCIe 6.0 PHY boasts state-of-the-art SI/PI performance, providing best-in-class design margin for first-time-right implementations.
Visit Rambus at booth #8 to see a hardware demonstration of these cutting-edge PCIe 6.0 Interface IP solutions. For more information on Rambus PCIe 6.0 IP, please visit this page.
